1. Field of the Invention
The present invention generally relates to the design of circuit components and more particularly, to the design of circuit components for accurately detecting asynchronous input signals in, for example, application specific integrated circuits (ASICs).
2. State of the Art
The use of asynchronous signals in electronic circuits and systems such as ASICs imposes signal detection considerations which must be taken into account to ensure proper circuit operation. Foremost among these considerations is the accurate detection of the asynchronous signal which, by definition, may occur at any point in time. Asynchronous signals occur when, for example, signals are transferred between circuits operating at different clock rates. These signals cannot be easily detected by strobing a given input at a predetermined time.
Further, the difficulty in detecting asynchronous signals is further enhanced by the unpredictable characteristics of the signal itself. For example, an asynchronous digital signal should have a sufficient pulse width to permit its ready detection. The pulse width of the signal represents the length of time during which a given logic level of the signal is available for detection. However, glitches in the signal can prevent signal detection circuitry from sensing the logic level of the signal for a long enough period of time to permit detection.
For example, a digital signal can be generated using an opaque disk with a light emitter and a light sensor. The opaque disk includes slits which permit light to pass through the disk from the emitter to the sensor. Light detected by the sensor is used to form pulses which represent an asynchronous signal. However, this form of digital generation is especially susceptible to the presence of glitches which prevent accurate signal detection.
Presently, circuits are known for detecting the logic state of asynchronous digital signals having unpredictable pulse widths. One such circuit is a common "D flip-flop" as shown in FIG. 1(a). An asynchronous signal to be detected is directed to the clock input 2 of the flip-flop, while a digital logic level to be detected is directed to the D input 4. The detected signal is then produced on the Q output line 6, after which the flip-flop is cleared via a reset line 8.
Another common circuit is a "set-reset latch" as shown in FIG. 1(b), wherein two NAND gates 10 and 12 are shown. Outputs of the two NAND gates are cross connected to a respective input of the opposite NAND gate. NAND gate 10 thus receives the output of NAND gate 12 and a reset signal as inputs. NAND gate 12 receives the output of NAND gate 10 and the asynchronous input signal as inputs.
In operation, an active low input signal is detected as follows. Initially, after a reset of the output of NAND gate 10 to an inactive high logic level, the reset line is held high. At this time the output of NAND gate 12 is low since the input signal is also in its inactive high logic state. The output of NAND gate 10 is therefore high since the reset input is high and the output of NAND gate 12 is low. When the asynchronous input signal goes low, the inputs of NAND gate 12 are no longer both high such that the output cf NAND gate 12 is driven high. When the output of NAND gate 12 goes high, both inputs of NAND gate 10 are high such that the output of NAND gate 10 is driven low.
A significant drawback of known signal detector designs such as those described above are their susceptibility to meta-stability. Meta-stability, as referred to herein, is the grey region which exists between a range of voltage values used to represent a logic low and a range of voltage values used to represent a logic high. If, for example, the pulse width and/or amplitude of an input signal is not of adequate duration or magnitude to permit the FIG. 1(b) circuitry to detect a logic level shift, then the FIG. 1(b) circuitry can, and often does, provide an output which floats in a meta-stable range of values. These meta-stable values are subsequently detected and interpreted as different logic level states by different circuits connected to the output and can cause significant circuit problems.
Accordingly, there is a need for a signal detector which is not susceptible to meta-stability and which provides accurate, reliable detection of logic level states associated with asynchronous signals of unpredictable pulse widths and amplitudes.